MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2214

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
2214
FIFO_SERVICE_
BITCLK_BASE_
FIFO_ERROR_
LRCLK_PULSE
NUM_SELECT
BIT_ORDER
CHANNEL_
DMAWAIT_
RSRVD2
IRQ_EN
IRQ_EN
COUNT
DELAY
23 21
20 16
15 14
RATE
Field
26
25
24
13
12
11
When the SAIF_BITCLK_MCLK pin is used as MCLK (and the alternate BITCLK pin mux function is enabled),
any oversample rate can be selected as dictated by the codec's required MCLK frequency.
Note that the clock controller block should be programmed with the correct DIV value to produce the correct
oversample clock base frequency (either 512x or 384x the sample rate) to the SAIF.
BITCLK Base Rate. This bit selects the base frequency rate at which the BITCLK pin toggles when configured
as an output (either in transmit mode or in receive master clock mode), or if the alternate BITCLK pin is
used, it selects the base frequency rate at which both the MCLK and alternate BITCLK pin toggles.
0 = BITCLK/MCLK base frequency rate is in multiples of 32x the sample rate.
1 = BITCLK/MCLK base frequency rate in in multiples of 48x the sample rate.
This bit field is used in conjunction with the BITCLK_MULT_RATE field to program the BITCLK/MCLK output
frequency.
Set this bit to one to enable a SAIF interrupt request on FIFO overflow or underflow status condition.
Set this bit to one to enable a SAIF interrupt request to service the FIFO when it contains an empty entry
(for transmit) or a full entry (for receive).
Reserved.
DMA Request Delay Count. This bit field specifies the number of APBX clock cycles (0 to 31) to delay after
a DMA request has been serviced and before the next request is granted. This field acts as a throttle on the
bandwidth consumed by the SAIF block. This field can be loaded by the DMA.
Channel Number Select. This bit field selects the number of channel pairs (left and right) that are transmitted
and/or received by the SAIF.
00 = One channel pair (stereo)
01 = Two channel pairs (front, surround)
10 = Three channel pairs (front, surround, center/lfe)
11 = Reserved
SAIF LRCLK Pulse Select. This bit used for the PCM Format where the LRCLK is high for one BITCLK cycle
at the beginning of the left PCM sample only.
0 = LRCLK toggles between Left and Right PCM samples
1 = LRCLK pulses high for 1 Bitclk cycle at the beginning of a PCM sample pair (left,Right).
SAIF PCM Data Serial Bit Order. This bit selects whether PCM data is serially transmitted or received LSB
or MSB first.
0 = MSB first
1 = LSB first
Note that the two's complement audio data written to and read from the FIFO is always ordered MSB to LSB
(LSB located in bit 0 for 17-bit through 24-bit operation, and in bits 15 and 0 for 16-bit operation).
SAIF Data Delay. In left-justified mode, this bit selects whether or not serial PCM data transmission/reception
is delayed by one BITCLK period each LRCLK frame (to generate I2S serial operation).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SAIF_CTRL field descriptions (continued)
Description
Freescale Semiconductor, Inc.