MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1021

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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13.2.7.4 Multi-Buffer Scatter/Gather Cipher and Hash Operation
For this example, three separate buffers are encrypted and hashed with the results being
directed to a unified buffer (gather operation). Three descriptors are used for the operation
because there are three separate source buffer pointers. The DCP reads data from the source
buffer and computes a hash on the unencrypted data. It then encrypts the data and writes it
to the destination buffer. For this example, the key is located in the key RAM, and the
algorithm uses the AES CBC mode of operation with a SHA-1 hash. The payload for the
first operation contains the CBC initialization value, and the payload for the last packet
contains the expected hash value. The middle packet requires no payload. This process is
illustrated below.
Freescale Semiconductor, Inc.
payload[4]=0x00112233;
payload[5]=0x44556677;
payload[6]=0x8899aabb;
payload[7]=0xccddeeff;
// set up control packet
dcp1.next = 0;
dcp1.ctrl0.U = 0;
dcp1.ctrl0.B.PAYLOAD_KEY = 1;
dcp1.ctrl0.B.CIPHER_ENCRYPT = 1; // encryption operation
dcp1.ctrl0.B.CIPHER_INIT = 1;
dcp1.ctrl0.B.ENABLE_CIPHER = 1;
dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore
dcp1.ctrl0.B.INTERRUPT = 1;
dcp1.ctrl1.U = 0;
dcp1.ctrl1.B.CIPHER_MODE = 1;
dcp1.src = srcbuffer;
dcp1.dst = dstbuffer;
dcp1.buf_size = 512;
dcp1.payload = payload;
dcp1.status = 0;
// Enable channel 0
HW_DCP_CHnCMDPTR_WR(0, dcp1);
HW_DCP_CHnSEMA_WR(0, 1);
// now wait for interrupt or poll
// polling code
while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 );
// now check/clear channel status
if ( (HW_DCP_CHnSTAT_RD(0) & 0xFF) != 0 ) {
}
// clear interrupt register
HW_DCP_STAT_CLR(1);
// an error occurred
HW_DCP_CHnSTAT_CLR(0, 0xff);
Programming Example
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
// CBC initialization
// single packet in chain
// clear ctrl0 field
// key is located in payload
// init CBC for this block (from payload)
// enable cipher
// interrupt
// clear ctrl1
// select CBC mode of operation
// source buffer
// destination buffer
// 512 bytes
// holds key/CBC init
// clear status
// write packet address to pointer register
// increment semaphore by 1
Chapter 13 Data Co-Processor (DCP)
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