MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1136

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
14.8.31 DRAM Control Register 33 (HW_DRAM_CTL33)
This is a DRAM configuration register.
Address:
1136
Reset
Reset
REG_DIMM_
OBSOLETE
Bit
Bit
W
W
ENABLE
R
R
REDUC
RSVD2
RSVD1
31 16
Field
15 9
7 1
8
0
31
15
0
0
HW_DRAM_CTL33
30
14
0
0
Always write zeroes to this field.
Always write zeroes to this field.
Enable the half datapath feature of the controller.
Controls the width of the memory datapath. When enabled, the upper half of the memory buses (DQ, DQS
and DM) are unused and relevant data only exists in the lower half of the buses. This parameter expands
the EMI for use with memory devices of the configured width or half of the configured width.
The entire user datapath is used regardless of this setting.
'b0 = Standard operation using full memory bus.
'b1 = Memory datapath width is half of the maximum size. The upper half of the data_byte_disable bus will
be driven to 'b1.
Always write zeroes to this field.
Enable registered DIMM operation of the controller.
Enables registered DIMM operations to control the address and command pipeline of the EMI.
'b0 = Normal operation
'b1 = Enable registered DIMM operation
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RSVD2
28
12
0
0
HW_DRAM_CTL32 field descriptions
800E_0000h base + 84h offset = 800E_0084h
27
11
0
0
26
10
0
0
25
0
0
9
OBSOLETE
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
RSVD1
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
AP
16
0
0
0