MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1952

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Programmable Registers
30.4.7 UART Data Register (HW_UARTAPP_DATA)
The UART Data Register is the receive and transmit data register. Receive (read) and
transmit (write) up to four data characters per APB cycle.
For words to be transmitted: 1) If the FIFOs are enabled, data written to this location is
pushed onto the transmit FIFO; 2) If the FIFOs are not enabled, data is stored in the
transmitter holding register (the bottom word of the transmit FIFO). The write operation
1952
DCDMIEN
CTSMIEN
DSRMIS
DCDMIS
CTSMIS
RIMIEN
RSVD2
ABDIS
15 12
RIMIS
OEIS
BEIS
PEIS
RTIS
RXIS
Field
FEIS
TXIS
18
17
16
11
10
9
8
7
6
5
4
3
2
1
0
nUARTDCD Modem Interrupt Enable. This bit is not supported.
nUARTCTS Modem Interrupt Enable.
nUARTRI Modem Interrupt Enable. This bit is not supported.
Reserved, read as zero, do not modify.
Automatic Baudrate Detected Interrupt Status. To clear this bit, write the bit-clear address with the particular
bit set to 1.
Overrun Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
Break Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
Parity Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
Framing Error Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
Receive Timeout Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
Transmit Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
Receive Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set to 1.
nUARTDSR Modem Interrupt Status. This bit is not supported.
nUARTDCD Modem Interrupt Status. This bit is not supported.
nUARTCTS Modem Interrupt Status. To clear this bit, write the bit-clear address with the particular bit set
to 1.
nUARTRI Modem Interrupt Status. This bit is not supported.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_UARTAPP_INTR field descriptions (continued)
Description
Freescale Semiconductor, Inc.

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