MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1066

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

EMI AHB and AXI Interface
14.4 EMI AHB and AXI Interface
This section discusses how to cofingure and use the EMI AHB and AXI interface.
14.4.1 AHB-AXI Bridges
An incoming AHB transaction is translated to an AXI command in the AHB-AXI bridge.
The AHB-AXI bridges support the AHB-lite protocol and are designed for multilayer AHB
architectures. This implies that an AHB slave port never responds with a SPLIT or a RETRY
response type. Early termination of AHB bursts is fully supported.
Note that an the AHB slave port can be used in a system with masters that support the full
AHB protocol as long as the system is multilayer AHB. For simplicity, the AHB-AXI
bridges do not support exclusive access or lock accesses.
14.4.2 AXI Interfaces
The AXI interfaces function as AXI slaves to the AHB-AXI bridges. Transfers are
burst-based of variable byte counts. The transfer types INCR and WRAP are fully supported.
FIXED burst types are not supported.
Each interface contains five separate channels of traffic to/from the memory: write response,
read command, write command, read data, and write data.
14.4.2.1 Internal Command Handling
The EMI uses placement logic to fill the command queue with a command order that
maximizes the throughput and efficiency of the core logic. Command reordering in the
placement queue supports AXI and AHB restrictions.
Note: The AHB bus does not allow multiple threads on a single port; therefore, ports with
an AHB-AXI bridge only use thread ID “0” for all commands.
Note: For simplicity, ports that connect to an AHB bus through an AHB-AXI bridge will
be referenced as “AHB-bridged” ports. Ports that connect directly to an AXI bus will be
referenced as “native AXI” ports.
If the placement logic is being used, the EMI will optimize the core by re-ordering read and
write commands as necessary based on these rules:
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1066
Freescale Semiconductor, Inc.