MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 858

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
10.8.2 System PLL0, System/USB0 PLL Control Register 1
PLL0 Lock Control Register
The lock count is driven off of xtal. So after the PLL0 is powered on, the PLL0 Lock should
be asserted after 50 us.
EXAMPLE
HW_CLKCTRL_PLL0CTRL1_WR(BF_CLKCTRL_PLL0CTRL1_FORCE_LOCK(1));
Address:
858
Reset
Reset
EN_USB_CLKS
force pll lock
Bit
Bit
W
W
RSRVD1
POWER
R
R
Field
16 0
18
17
LOCK
31
15
0
0
(HW_CLKCTRL_PLL0CTRL1)
HW_CLKCTRL_PLL0CTRL1 8004_0000h base + 10h offset = 8004_0010h
30
14
0
0
0: 8-phase PLL outputs for USB0 PHY are powered down. If set to 1, 8-phase PLL outputs for USB0 PHY
are powered up. Additionally, the utmi clock gate must be deasserted in the UTMI0 phy to enable USB0
operation. If HW_USBPHY_CTRL.ENAUTOSET_USBCLKS of USB0 is set, this bit will be set automatically
when USB0 remote wakeup event happens.
PLL Power On (0 = PLL off; 1 = PLL On). Allow 10 us after turning the PLL0 on before using the PLL0 as a
clock source. This is the time the PLL0 takes to lock to 480 MHz. If
HW_USB_PHY_CTRL_ENAUTO_PWRON_PLL of UTM0 is set, this bit will be set to one (1'b1) automatically
when either USB0 or USB1 remote wakeup event happens. Note: The POWER bit must be set to on to
ungate the reference xtal to all of the PLLs.
Always set to zero (0).
HW_CLKCTRL_PLL0CTRL0 field descriptions (continued)
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_PLL0CTRL1_WR(BF_CLKCTRL_PLL0CTRL1_FORCE_LOCK(0));
28
12
0
0
27
11
0
0
26
10
0
0
25
0
0
9
LOCK_COUNT
24
0
0
8
Description
23
RSRVD1
0
0
7
22
0
0
6
// force pll lock sequence
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
// clear
16
0
0
0