MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1559

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Once the MB is activated in the fourth step, it will participate in the arbitration process and
eventually be transmitted according to its priority. At the end of the successful transmission,
the value of the Free Running Timer is written into the Time Stamp field, the Code field in
the Control and Status word is updated, a status flag is set in the Interrupt Flag Register and
an interrupt is generated if allowed by the corresponding Interrupt Mask Register bit. The
new Code field after transmission depends on the code that was used to activate the MB in
step four (see
Abort feature is enabled (AEN in MCR is asserted), after the Interrupt Flag is asserted for
a MB configured as transmit buffer, the MB is blocked, therefore the ARM is not able to
update it until the Interrupt Flag be negated by ARM. It means that the ARM must clear
the corresponding IFLAG before starting to prepare this MB for a new transmission or
reception.
25.4.3 Arbitration Process
The arbitration process is an algorithm executed by the MBM that scans the whole MB
memory looking for the highest priority message to be transmitted. All MBs programmed
as transmit buffers will be scanned to find the lowest ID
highest priority, depending on the LBUF and LPRIO_EN bits on the Control Register. The
arbitration process is triggered in the following events:
1.
Freescale Semiconductor, Inc.
Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at
the same positions they are transmitted in the CAN frame.
• If the MB is active (transmission pending), write an ABORT code ('1001') to the Code
• Write the ID word.
• Write the data bytes.
• Write the Length, Control and Code fields of the Control and Status word to activate
• During the CRC field of the CAN frame
• During the error delimiter field of the CAN frame
field of the Control and Status word to request an abortion of the transmission, then
read back the Code field and the IFLAG register to check if the transmission was aborted
(see
MCR negated), just write '1000' to the Code field to inactivate the MB but then the
pending frame may be transmitted without notification (see
Deactivation).
the MB.
Transmission Abort
Table 25-2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
and
Mechanism). If backwards compatibility is desired (AEN in
Table 25-3
in Section
Message Buffer
Chapter 25 Controller Area Network (FlexCAN)
1
or the lowest MB number or the
Message Buffer
Structure). When the
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