MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1184

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
14.8.87 DRAM Control Register 92 (HW_DRAM_CTL92)
This is a DRAM configuration register.
Address:
Re-
14.8.88 DRAM Control Register 93 (HW_DRAM_CTL93)
This is a DRAM configuration register.
Address:
Re-
1184
set
set
Bit
Bit
W
W
R
R
DLL_CTRL_
DLL_CTRL_
REG_1_1
REG_1_2
31
31
0
0
Field
31 0
Field
31 0
30
30
0
0
29
29
0
0
HW_DRAM_CTL92
HW_DRAM_CTL93
28
28
0
0
Holds the clk_wr settings and the Dll increment value for data slice 1.
There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus.
Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X
[28] = 'b1) Each increment of this field represents 1/128th of a clock cycle.
Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value
is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle.
Bits [7:0] = DLL Increment Value. This sets the increment used by the DLL when searching for a lock. It is
recommended to keep this field small (around 0x4) to keep the steps gradual.
All other bits undefined.
Holds the clk_wr settings and the Dll increment value for data slice 2.
There is a separate dll_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus.
Bits [23:15] = Holds the clk_wr delay setting when the DLL is operating in bypass mode. (dll_ctrl_reg_0_X
[28] = 'b1) Each increment of this field represents 1/128th of a clock cycle.
Bits [14:8] = Holds the clk_wr delay setting in normal mode. (dll_ctrl_reg_0_X [28] = 'b0) Typically, this value
is 3/4 of a clock cycle. Each increment of this field represents 1/128th of a clock cycle.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
HW_DRAM_CTL92 field descriptions
HW_DRAM_CTL93 field descriptions
800E_0000h base + 170h offset = 800E_0170h
800E_0000h base + 174h offset = 800E_0174h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
DLL_CTRL_REG_1_1
DLL_CTRL_REG_1_2
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0