MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1854

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
29.9.10 ENET SWI Define behavior of VLAN input manipulation function
Define behavior of VLAN input manipulation function, if such a function is present on an
input port.
Each input port can operate in one of four modes individually defining 2 bits per port: "00":
Mode 1, Single Tag passthrough "01": Mode 2, Single Tag overwrite "10": Mode 3, Double
Tag passthrough "11": Mode 4, Double Tag overwrite The settings have effect only, when
enabled by setting the corresponding bit in VLAN_IN_MODE_ENA below.
Address:
1854
Reset
SWITCH_RESET
SWITCH_EN
STOP_EN
Bit
W
RSRVD0
R
Field
6 2
7
1
0
31
0
HW_ENET_SWI_VLAN_IN_MODE 800F_8000h base + 28h offset = 800F_
8028h
(HW_ENET_SWI_VLAN_IN_MODE)
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0
HW_ENET_SWI_MODE_CONFIG field descriptions (continued)
When disabled (0, default) the output pins ff_rx_crc_fwd1/2 to the MACs are always 0 to ensure a CRC is
appended to outgoing frames no matter from which port they were received. DMA0 still can influence the
crc append through its ff_tx_crc_fwd0 input pin if required.
Note: The ff_tx_crc_fwd0 input to the switch must be valid throughout the complete frame (from sop to eop).
This is in contrast to the MAC definition for this signal, which requires validity during eop only.
Controls toplevel output pin stop_en.
No internal function.
Reserved bits. Write as 0.
Controls toplevel output pin switch_en.
When deasserted (0), all DMA registers are cleared.
Controls toplevel output pin switch_reset.
No internal function.
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0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
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0
27
0
26
0
25
0
RSRVD0[31:16]
24
0
Description
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0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
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0
18
0
17
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16
0