MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1019
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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<code>
typedef struct _dcp_descriptor
{
}
Freescale Semiconductor, Inc.
DCP_DESCRIPTOR dcp1;
u32 *srcbuffer;
u32 payload[5];
// set up expected hash check value
payload[0]=0x01234567;
payload[1]=0x89ABCDEF;
payload[2]=0x00112233;
payload[3]=0x44556677;
payload[4]=0x8899aabb;
// set up control packet
dcp1.next = 0;
dcp1.ctrl0.U = 0;
dcp1.ctrl0.B.HASH_CHECK = 1;
dcp1.ctrl0.B.HASH_INIT = 1;
dcp1.ctrl0.B.HASH_TERM = 1;
dcp1.ctrl0.B.ENABLE_HASH = 1;
dcp1.ctrl0.B.DECR_SEMAPHORE = 1; // decrement semaphore
dcp1.ctrl0.B.INTERRUPT = 1;
dcp1.ctrl1.U = 0;
dcp1.src = srcbuffer;
dcp1.dst = 0;
dcp1.buf_size = 512;
dcp1.payload = payload;
dcp1.status = 0;
// Enable channel 0
HW_DCP_CHnCMDPTR_WR(0, dcp1);
HW_DCP_CHnSEMA_WR(0, 1);
// now wait for interrupt or poll
// polling code
while ( (HW_DCP_STAT_RD() & 0x01) == 0x00 );
DCP_DESCRIPTOR;
u32
hw_dcp_packet1_t
hw_dcp_packet2_t
u32
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
*next;
*src,
*dst,
*payload,
ctrl0;
ctrl1;
buf_size,
stat;
0x70 = Hash Check | Hash Term | Hash Init
0x43 = Hash Enable | DecrSema | Interrupt
Next
Ctrl0
Ctrl1
Src
Dst
Bytes
Payld
Stat
Figure 13-11. Basic Hash Operation
Tag
Source Buffer Address
Payload Addrses
// single packet in chain
// clear ctrl0 field
// check hash when complete
// initialize hash with this block
// terminate hash with this block
// enable hash
// interrupt
// clear ctrl1
// source buffer
// no destination buffer
// 512 bytes
// holds expected hash value
// clear status
// write packet address to pointer register
// increment semaphore by 1
SHA1
Byte Count
0x70
0x43
Expected
Payload
Hash
Source
Buffer
Chapter 13 Data Co-Processor (DCP)
1019
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