MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1179

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.8.80 DRAM Control Register 85 (HW_DRAM_CTL85)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
PAD_CTRL_
31
0
REG_0
Field
31 0
30
0
29
0
HW_DRAM_CTL85
28
0
Controls pad termination, type and IDDQ settings.
These bit settings are specific to the pad models included with this PHY. The user should alter the
programming relative to the particular pads being used in their design.
EMI provides a dynamic termination signal tsel that provides one bit per byte of memory data. The user
must attach this signal to the pads dependent on pad requirements.
Bit [12] = Defines the pad impedance if the parallel termination option is enabled. Default 'b1.
'b0 = 75 Ohm
'b1 = 150 Ohm
Bit [8] = Defines the pad type. Default 'b1.
'b0 = DDR1
'b1 = DDR2
Bit [5] = Defines the IDDQ_RX select for the signal pads. Default 'b1.
'b0 = Do not feed input into IDDQ
'b1 = Feed input into IDDQ
Bit [4] = Defines the IDDQ_TX select for the signal pads. Default 'b1.
'b0 = Do not feed output into IDDQ
'b1 = Feed output into IDDQ
Bit [1] = Defines the IDDQ_RX select for the clock pads. Default 'b1.
'b0 = Do not feed input into IDDQ
'b1 = Feed input into IDDQ
Bit [0] = Defines the IDDQ_TX select for the clock pads. Default 'b1.
'b0 = Do not feed output into IDDQ
'b1 = Feed output into IDDQ
All other bits Reserved.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL85 field descriptions
800E_0000h base + 154h offset = 800E_0154h
22
0
21
0
20
0
19
0
18
0
PAD_CTRL_REG_0
17
0
16
0
15
0
Description
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1179
0
0