MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1533

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

24.2.6 Disabling the FIFOs
FIFOs can be disabled. In this case, the transmit and receive sides of the UART have one-byte
holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has
been received and the previous one was not yet read.
In this implementation, the FIFOs are not physically disabled, but the flags are manipulated
to give the illusion of a one-byte register.
24.3 Programmable Registers
UARTDBG Hardware Register Format Summary
Freescale Semiconductor, Inc.
8007_402C
8007_4000
8007_4004
8007_4018
8007_4020
8007_4024
8007_4028
8007_4030
8007_4034
Absolute
address
(hex)
FIFO bit
7:0
11
10
9
8
UART Data Register (HW_UARTDBG_DR)
UART Receive Status Register (Read) / Error Clear Register
(Write) (HW_UARTDBG_ECR)
UART Flag Register (HW_UARTDBG_FR)
UART IrDA Low-Power Counter Register
(HW_UARTDBG_ILPR)
UART Integer Baud Rate Divisor Register
(HW_UARTDBG_IBRD)
UART Fractional Baud Rate Divisor Register
(HW_UARTDBG_FBRD)
UART Line Control Register, HIGH Byte (HW_UARTDBG_H)
UART Control Register (HW_UARTDBG_CR)
UART Interrupt FIFO Level Select Register
(HW_UARTDBG_IFLS)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 24-1. Receive FIFO Bit Functions
Register name
HW_UARTDBG memory map
Overrun indicator
Received data
Framing error
Break error
Parity error
Function
(in bits)
Width
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Chapter 24 Debug UART (DUART)
R
Reset value
0000_0000h
0000_0000h
0000_0090h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0300h
0000_0012h
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