MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2241

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 37 High-Speed ADC (HSADC)
37.2.2 Trigger Modes
This block can be triggered to start the conversion of analog source by three modes: the
first mode is software trigger mode which is to trigger it by ARM CPU to configure a register
bit in this block; the second mode is to trigger it by a trigger signal which is generated by
the PWM block with big flexibility; the third is to trigger it by an input pin from external
sources to support some general user cases.
37.2.3 APBH-DMA Channel
This block is connected to a channel of APBH-DMA to move the sample data from the
16x32 asynchronous FIFO inside the block to the external memory. The APBH-DMA can
run at up to 200 MHz clock frequency to reduce the possibility of FIFO overflow. The DMA
can also offload the loading of ARM core when the high-speed ADC is working in the loop
mode.
37.2.4 Synchronization with PWM Block
This block uses an operation clock the same as the PWM block. It can make it possible that
the PWM generate driving signals of external devices and then keep synchronous with
high-speed ADC. This will improve the design flexibilities. By selecting the trigger mode
of PWM trigger, the high-speed ADC can co-work with the PWM block to support many
different user cases.
37.2.5 Clock Domains
This block includes two clock domains. One is the AHB clock domain which is synchronous
with the APBH clock. The other is operation clock domain which is the same as the analog
operation clock. The AHB clock domain can run at up to 200 MHz clock frequency while
the operation clock domain can only run at up to 32 MHz clock frequency. The operation
clock needs to be with duty cycle ratio of 25%.
37.2.6 Sample Precision, Endian, Half-word Swap and Bits Left-Shift
The original output of the analog ADC block is 12-bit data. The user can configure the
register to get 12-bit,10-bit or 8-bit sample data. For 12-bit or 10-bit modes, two samples
are combined to be a 32-bit word. For 8-bit mode, four samples are combined to be a 32-bit
word. When using 8-bit mode or 10 bit mode, the user can select any consequential 8 bit
or 10 bit sample data from the 12-bit sample data by configuring the register. The sample
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
2241