MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1992

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
31.7.23 Next Asynchronous Address Register (Host Controller mode)
In Host Controller mode, this 32-bit register contains the address of the next asynchronous
queue head to be executed by the host. Bits [4:0] of this register cannot be modified by the
system software and will always return a 0 when read.
Address:
Re-
1992
set
Bit
W
R
USBADRA
ASYBASE
USBADR
31
0
31 25
RSVD
Field
23 0
Field
31 5
24
30
0
29
0
HW_USBCTRL_ASYNCLISTADDR
0158h
(HW_USBCTRL_ASYNCLISTADDR)
28
0
Device Address.
These bits correspond to the USB device address.
Device Address Advance.
Default=0.
When this bit is `0', any writes to USBADR are instantaneous.
When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field
is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be
loaded from the holding register.
Hardware will automatically clear this bit on the following conditions:
1. IN is ACKed to endpoint 0. (USBADR is updated from staging register).
2. OUT/SETUP occur to endpoint 0. (USBADR is not updated).
3. Device Reset occurs (USBADR is reset to 0). Note: After the status phase of the SET_ADDRESS descriptor,
the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when
the DCD cannot write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD
writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status
phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement.
Reserved.
Must be written as zeros. During runtime, the values of these bits are undefined.
Link Pointer Low (LPL).
These bits correspond to memory address signals [31:5], respectively.This field may only reference a Queue
Head (OH). Only used by the host controller.
27
0
26
0
HW_USBCTRL_ASYNCLISTADDR field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_USBCTRL_DEVICEADDR field descriptions
24
0
23
0
22
0
21
0
20
0
ASYBASE
19
0
8008_0000h base + 158h offset = 8008_
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
RSVD
0
2
0
1
0
0