MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2291

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

38.5.10 LRADC 4 Result Register (HW_LRADC_CH4)
The LRADC result register returns the 12-bit result for low resolution analog to digital
converter channel four.
HW_LRADC_CH4: 0x090
HW_LRADC_CH4_SET: 0x094
HW_LRADC_CH4_CLR: 0x098
HW_LRADC_CH4_TOG: 0x09C
The Result register contains the most recent conversion results for one channel of the
LRADC. Note that each channel can be converted at an independent rate. The TOGGLE
bit is used to debug missed conversion cycles. When using oversampling, the channel must
be individualy scheduled for conversion N times for when N samples are required before
an interrupt is generated. This is most easily accomplished by using one of the LRADC
Delay Channels.
EXAMPLE
if (HW_LRADC_CHn(4).TOGGLE == 1) { } // Toggle is high.
// ...
unsigned long channelAverage;
HW_LRADC_CHn_WR(4, (BF_LRADC_CHn_ACCUMULATE(1)
// ... setup Delay channel (see HW_LRADC_DELAY0 through 3)
while (HW_LRADC_CTRL1.LRADC4_IRQ != BV_LRADC_CTRL1_LRADC4_IRQ__PENDING)
{
Freescale Semiconductor, Inc.
NUM_SAMPLES
ACCUMULATE
RSRVD1
VALUE
28 24
23 18
Field
17 0
29
Set this bit to one to add successive samples to the 18 bit accumulator.
This bit field contains the number of conversion cycles to sum together before reporting operation complete
interrupt status. Set this field to zero for a single conversion per interrupt.
Reserved
This bit field contains the most recent 12-bit conversion value for this channel. If automatic oversampling is
enbled this bit field contains the sum of the most recent N oversampled values, where N is set in the
NUM_SAMPLES field for this channel. When 32 full-scale samples are added together, the 12-bit results
can sum up to 256K. Software is responsible for dividing this value by the number of samples summed
together. Software must clear this register in preparation for a multi-cycle accumulation.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BF_LRADC_CHn_NUM_SAMPLES(5)
BF_LRADC_CHn_VALUE(0) ) );
HW_LRADC_CH3 field descriptions (continued)
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
Description
| // Enable accumulation mode.
| // Set samples to five.
// Clear accumulator.
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