MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1188

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
14.8.94 DRAM Control Register 99 (HW_DRAM_CTL99)
This is a DRAM configuration register.
Address:
Re-
14.8.95 DRAM Control Register 100 (HW_DRAM_CTL100)
This is a DRAM configuration register.
Address:
Re-
1188
set
set
Bit
PHY_OBS_REG_
Bit
W
W
R
R
31
31
0
0
Field
31 0
0_0
30
30
0
0
29
29
0
0
HW_DRAM_CTL99
HW_DRAM_CTL100
28
28
0
0
Controls loopback status, data and masking info for slice 0. READ-ONLY
Reports status for the PHY.
Bit [24] = Status signal to indicate that the logic gate had to be forced closed.
'b0 = Normal operation
'b1 = Gate close was forced
Bits [23:8] = Loopback data. Reports the actual data or expected data, depending on the setting of the
phy_ctrl_reg_1_X [20] parameter bit.
Bits [5:4] = Loopback mask data. Reports the actual data mask or the expected data mask, depending on
the setting of the phy_ctrl_reg_1_X [20] parameter bit.
Bit [1] = Reports status of loopback errors.
'b0 = Last Loopback test had no errors.
'b1 = Last Loopback test contained data errors.
Bit [0] = Defines the status of the loopback mode.
'b0 = Not in loopback mode.
'b1 = In Loopback mode.
All other bits Reserved.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
HW_DRAM_CTL99 field descriptions
800E_0000h base + 18Ch offset = 800E_018Ch
800E_0000h base + 190h offset = 800E_0190h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
PHY_OBS_REG_0_0
PHY_OBS_REG_0_1
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0