MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2226

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
A module-level reset is also provided in HW_SPDIF_CTRL_SFTRST. Setting this bit
performs a module-wide reset and subsequent assertion of the
HW_SPDIF_CTRL_CLKGATE.
36.2.3 DMA Operation
Using the SPDIF module in DMA mode involves configuring the appropriate DMA channel
to provide the interleaved data blocks stored in memory. See
Overview
engine references a set of linked DMA descriptors stored by the CPU in main memory.
These descriptors point to data blocks stored in system memory and also provide a
mechanism for automated PIO writes before transfer of a data-block.
a typical set of descriptors required to transmit two data-blocks.
2226
for detailed information on DMA programming. Once programmed, the DMA
A soft reset (SFTRST) can take multiple clock periods to
complete, so do NOT set CLKGATE when setting SFTRST. The
reset process gates the clocks automatically. See
Soft Reset a Block
SFTRST and CLKGATE bit fields.
Figure 36-3. SPDIF DMA Two-Block Transmit Example
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SPDIF_CTRL=0x00000002
read
HW_SPDIF_FRAMECTRL=
BUFFER ADDRESS
512
NEXTCMD_ADDR
0x00030000
512-Byte
Block 0
Data
2
0
0
for additional information on using the
1
10
HW_SPDIF_CTRL=0x00000002
HW_SPDIF_FRAMECTRL=
read
_
BUFFER ADDRESS
512
NEXTCMD_ADDR
Note
0x00030000
512-Byte
Block 1
Data
2
0
0
1
10
HW_SPDIF_CTRL=0xC0000000
BUFFER ADDRESS
NEXTCMD_ADDR
0
AHB-to-APBX Bridge
Correct Way to
1
0
0
Figure 36-3
Freescale Semiconductor, Inc.
1
10
describes