MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1624

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
MAC Receive
26.3.7.3 Preamble Processing
The IEEE 802.3 Standard allows a maximum size of 56 bits (7 bytes) for the preamble,
while the MAC Core allows any arbitrary preamble length. The MAC Core checks for the
start frame delimiter (SFD) byte. If the next byte of the preamble, which is different from
0x55, is not 0xD5, the frame will be discarded.
Although the IEEE specification specifies that Frames should be separated at least by 96
bit (Inter Packet Gap or IPG), the MAC Core is designed to accept frames only separated
by 64 MII (10/100Mbps operation) bits.
The MAC Core removes all the preamble bytes and the SFD byte.
26.3.7.4.1 Overview
The destination address bit 0 is used to differentiate Multicast and Unicast Addresses:
26.3.7.4.2 Unicast Address Check
If a Unicast address is received, the destination MAC address is compared to the Node
MAC address programmed by the host in the registers PADDR1/PADDR2. In addition, it
is compared to the supplemental MAC addresses programmed in the registers
SMAC_0_0/SMAC_0_1, SMAC_1_0/SMAC_1_1, SMAC_2_0/SMAC_2_1 and
SMAC_3_0/SMAC_3_1. If the destination address matches any of the programmed MAC
addresses, the frame is accepted.
If only one MAC address is required, all the supplemental MAC addresses should be
programmed with the Node MAC address.
If promiscuous mode is enabled (configuration register RCR(PROM) set to '1' ) no address
checking is performed and all Unicast frames are accepted.
26.3.7.4.3 Multicast and Unicast Address Resolution
The hash table algorithm used in the group and individual hash filtering operates as follows.
The 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored
in GAUR, GALR (group address hash match), or IAUR, IALR (individual address hash
match). This mapping is performed by passing the 48-bit address through the on-chip 32
bit CRC generator and selecting the six most significant bits of the CRC-encoded result to
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• If bit 0 is set '0' the MAC address is an individual (Unicast) address.
• If bit 0 is set '1' the MAC address defines a group address (Multicast Address).
• If all 48 bits of the MAC address are set to '1' it indicates a Broadcast address.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.

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