MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1613

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

26.3.4.2 Pause Frames
A Pause Frame is generated by the receiving device to indicate a congestion to the emitting
device which should stop sending data.
Pause Frames are indicated by the Length/Type set to 0x8808. The two first bytes of a Pause
Frame following the type, defines a 16-Bit opcode field set to 0x0001 always. A 16-Bit
Pause Quanta is defined in the Frame payload Bytes 2 (Byte P1) and 3 (Byte P2) as defined
in
There is no Payload Length field found within a Pause Frame and a Pause Frame is always
padded with 42 bytes (0x00).
If a pause frame with a pause value greater zero (XOFF Condition) is received, the MAC
stops transmitting data as soon the current Frame transfer is completed. The MAC stops
transmitting data for the value defined in pause quanta. One pause quanta fraction refers to
512 bit times.
If a pause frame with a pause value of zero (XON Condition) is received, the transmitter is
allowed to send data immediately (See chapter 10 for details).
26.3.4.3 Magic Packets
A Magic Packet can be a Unicast, Multicast or Broadcast packet, which carries a defined
sequence in the payload section. Magic Packet are received and inspected only under specific
conditions as described in
Freescale Semiconductor, Inc.
Table
55
15
00
69
26
1
26-6. The pause quanta byte P1 is the most significant.
6B
55
16
00
70
2
CRC-32
Source Address
AE
55
17
00
71
3
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Preamble
Table 26-6. Pause Frame Format (values in hex)
0A
55
18
00
72
4
Magic Packet Detection
55
19
00
5
55
20
00
6
55
21
88
7
Type
SFD
D5
22
08
8
01
23
00
9
Opcode
Multicast Destination Address
Chapter 26 Ethernet Controller (ENET)
10
80
24
01
C2
P1
11
25
hi
P2
12
00
26
lo
13
00
pad (42)
27-68
00
14
01
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