MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1763

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor, Inc.
CLK_GEN_BUSY
IRQ_SUMMARY
SLAVE_FOUND
DATA_ENGINE_
DATA_ENGINE_
DATA_ENGINE_
SLAVE_ADDR_
SLAVE_BUSY
CMPLT_IRQ_
SEARCHING
BUS_FREE_
DMA_WAIT
BUS_BUSY
SUMMARY
EQ_ZERO
SLAVE_
BUSY
Field
15
14
13
12
11
10
9
8
7
6
This read-only bit indicates that the I2C slave function was searching for a transaction that matches the
current slave address. When set to one, it indicates that an address match was found for the exact adderss
0x00.
0x0
0x1
This read-only bit indicates that the I2C slave function was searching for a transaction that matches the
current slave address. When set to one, it indicates that an address match was found and the I2C clock is
frozen by the slave search. This bit is cleared by starting the appropriate slave DMA transfer or restarting a
slave search.
0x0
0x1
This read-only bit indicates that the I2C slave function is searching for a transaction that matches the current
slave address.
0x0
0x1
This read-only bit is set to one when the data engine is waitng for data from a DMA device. This bit can be
used to transmit short I2C transactions without using a DMA channel. This generally works for up to three
data bytes transmitted with one address byte.
0x0
0x1
This read-only bit indicates that the I2C bus is busy with a transaction. It is set by a start condition and reset
by a detected stop condition.
0x0
0x1
This read-only bit indicates that the I2C clock generator is busy with a transaction.
0x0
0x1
This read-only bit indicates that the I2C data transfer engine is busy with a data transmit or recieve opertion.
In addition, it can be busy, as a master, sending a start or stop condition.
0x0
0x1
This read-only bit indicates that the I2C slave address search engine is busy with a transaction. This bit will
go high when an address search is started and will remain high until the slave search engine returns to its
idle state.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
ZERO_NOT_MATCHED — I2C slave search did not match a zero.
WAS_ZERO — I2C has found an address match against address 0x00.
IDLE — I2C slave search is idle.
WAITING — I2C has found an address match and is holding the I2C clock line low.
IDLE — I2C slave search is idle.
ACTIVE — I2C is actively searching for an address match.
CONTINUE — I2C master is not waiting on data from the DMA.
WAITING — I2C master is waiting on data from the DMA.
IDLE — I2C bus is idle, i.e. reset state or at least one stop condition detected.
BUSY — I2C bus is busy, i.e. at least one start condition has been detected.
IDLE — I2C clock generator is idle.
BUSY — I2C clock generator is busy performing a command.
IDLE — I2C Data Engine is idle.
BUSY — I2C is Data Engine busy performing a data transfer.
IDLE — I2C slave search engine is idle.
BUSY — I2C slave search engine is busy searching for an address match.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_I2C_STAT field descriptions (continued)
Description
Chapter 27 Inter IC (I2C)
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