MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1661
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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26.4.1 ENET MAC Interrupt Event Register (HW_ENET_MAC_EIR)
When an event occurs that sets a bit in HW_ENET_MAC_EIR, an interrupt occurs if the
corresponding bit in the interrupt mask register (HW_ENET_MAC_EIMR) is also set.
Writing a 1 to an HW_ENET_MAC_EIR bit clears it; writing 0 has no effect. This register
is cleared upon hardware reset.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
800F_0684
Absolute
address
Bit
Bit
W
W
(hex)
RSRVD0
R
R
BABR
BABT
Field
31
30
29
31
15
0
0
HW_ENET_MAC_EIR
BABR
ENET MAC IEEE1588 Interrupt enable mask register
(HW_ENET_MAC_CCB_INT_MASK)
30
14
0
0
Reserved bits. Write as 0.
Babbling receive error. This bit indicates a frame was received with length in excess of MAX_FL bytes.
Babbling transmit error. This bit indicates the transmitted frame length exceeds MAX_FL bytes. This condition
usually caused by a frame that is too long placed into the transmit data buffer(s). Truncation does not occur.
BABT
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
GRA
28
12
0
0
HW_ENET_MAC_EIR field descriptions
HW_ENET memory map (continued)
Register name
TXF
800F_0000h base + 4h offset = 800F_0004h
27
11
0
0
TXB
26
10
0
0
RXF
25
0
0
9
RXB
24
0
0
8
RSRVD1
Description
MII
23
0
0
7
22
0
0
6
(in bits)
Width
32
LC
21
0
5
0
Chapter 26 Ethernet Controller (ENET)
Access
R/W
RL
20
0
4
0
Reset value
0000_0000h
UN
19
0
0
3
PLR
18
0
0
2
26.4.112/1727
17
0
0
1
Section/
page
1661
16
0
0
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