MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2093

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

33.4.8 LCDIF VSYNC Mode and Dotclk Mode Control Register0
This register is used to control the VSYNC and DOTCLK modes of the LCDIF so as to
work with different types of LCDs like moving picture displays and delta pixel displays.
HW_LCDIF_VDCTRL0: 0x070
HW_LCDIF_VDCTRL0_SET: 0x074
HW_LCDIF_VDCTRL0_CLR: 0x078
HW_LCDIF_VDCTRL0_TOG: 0x07C
This register gives general programmability to the VSYNC signal including polarity,
direction, pulse width, etc.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DATA_SETUP
CMD_SETUP
DATA_HOLD
Bit
Bit
W
W
RSRVD2
R
R
23 16
31 30
Field
15 8
Field
7 0
31
15
RSRVD2
0
0
(HW_LCDIF_VDCTRL0)
HW_LCDIF_VDCTRL0
30
14
0
0
Number of CLK_DIS_LCDIFn cycles that the the DCn signal is active before CEn is asserted.
Data bus hold time in CLK_DIS_LCDIFn cycles. Also the time that the data strobe is de-asserted in a cycle
Data bus setup time in CLK_DIS_LCDIFn cycles. Also the time that the data strobe is asserted in a cycle.
Reserved bits. Write as 0.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LCDIF_TIMING field descriptions (continued)
28
12
0
0
HW_LCDIF_VDCTRL0 field descriptions
27
11
0
0
8003_0000h base + 70h offset = 8003_0070h
26
10
0
0
VSYNC_PULSE_WIDTH[15:0]
25
0
0
9
24
0
0
8
Description
Description
23
RSRVD1
0
0
7
22
0
0
6
21
0
5
0
Chapter 33 LCD Interface (LCDIF)
20
0
4
0
19
0
0
3
18
0
0
2
WIDTH[17:16]
17
VSYNC_
0
0
PULSE_
1
2093
16
0
0
0