MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 604

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
604
Reset
WAIT4ENDCMD
XFER_COUNT
IRQONCMPLT
SEMAPHORE
CMDWORDS
COMMAND
Bit
W
R
RSVD1
RSVD0
CHAIN
31 16
15 12
11 8
Field
5 4
1 0
7
6
3
2
15
0
CMDWORDS
14
0
This field indicates the number of bytes to transfer to or from the appropriate PIO register in the UART1
device HW_UARTAPP_DATA register. A value of 0 indicates a 64 KBytes transfer.
This field indicates the number of command words to send to the UART1, starting with the base PIO address
of the UART1 (HW_UARTAPP_CTRL1) and increment from there. Zero means transfer NO command
words
Reserved, always set to zero.
A value of one indicates that the channel will wait for the end of command signal to be sent from the APBX
device to the DMA before starting the next DMA command.
A value of one indicates that the channel will decrement its semaphore at the completion of the current
command structure. If the semaphore decrements to zero, then this channel stalls until software increments
it again.
Reserved, always set to zero.
A value of one indicates that the channel will cause its interrupt status bit to be set upon completion of the
current command, i.e. after the DMA transfer is complete.
A value of one indicates that another command is chained onto the end of the current command structure.
At the completion of the current command, this channel will follow the pointer in HW_APBX_CH11_CMDAR
to find the next command.
This bitfield indicates the type of current command:
00- NO DMA TRANSFER
01- write transfers, i.e. data sent from the APBX device (APB PIO Read) to the system memory (AHB master
write).
10- read transfer
11- reserved
0x0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
NO_DMA_XFER — Perform any requested PIO word transfers but terminate command before any
DMA transfer.
12
0
HW_APBX_CH11_CMD field descriptions
11
0
10
0
RSVD1
0
9
0
8
Description
0
7
0
6
5
0
RSVD0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
COMMAND
0
1
0
0