MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 120
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 120 of 2327
- Download datasheet (17Mb)
Operation
3.2.1 Top-Level Symbol and Functional Overview
The DFLPT connects to the AHB as shown in
pipelining (single wait-state), the bus interfaces have little or no combinatorial logic. The
read and address paths connect directly to the registers. The write-path connects to the
register bank through one level 1-hot muxing. All address and locator decodes are also
performed using 1-hot logic. Offset address generated from the AHB address (for purposes
of generating spanned base addresses) use a registered version of the AHB address.
3.2.2 Memory Map
The virtual memory view of the DFLPT can be seen in the figure below. This example
shows how a MPTE can be spanned and how it will appear to the ARM MMU. In this
example, MPTE0 is set as follows:
120
• HW_DIGCTL_MPTE0_DIS = 0x0
• HW_DIGCTL_MPTE0_SPAN = 0x2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
ahb_wdata
ahb_ready_out
ahb_ready_in
ahb_rdata
ahb_trans,
ahb_write,
ahb_addr,
ahb_resp,
Figure 3-2. DFLPT System Level Block Diagram
APBH Bridge
MPTEn_LOC / SPAN
State Logic
Locate/Span
17:1 Read data
Logic
APBH
mux
Figure
DIGCTL
3-2. Note that due to the internal
Reg Select
Span base-addr Gen
MPTEn_DIS
Movable PTE regs
Entry 2048 (PIO)
(MPTE0-15)
+
DFLPT
Freescale Semiconductor, Inc.
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