MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1768

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Address:
1768
Reset
Reset
SEND_NAK_ON_
ACKNOWLEDGE
MULTI_MASTER
CLOCK_HELD
Bit
Bit
PRE_ACK
W
W
R
R
RSVD2
RSVD1
31 28
LAST
Field
27
26
25
24
23
22
31
15
0
0
HW_I2C_QUEUECMD
30
14
0
0
RSVD2
Always set this bit field to zero.
Reserved for Freescale use.
Set this bit to one to cause a pending acknowledge bit (prior to DMA transfer) to be acknowledged. Set it
to zero to NAK the pending acknowledge bit. This bit is set to one by the slave search engine if the criteria
is met for acknowledging a slave address. Software can reset the bit to slave-not-acknowledge the address.
This bit defines the state of the i2c_data line during the address acknowledge bit time. The slave search
engine holds the clock at this point for a software decision. This bit has no effect when the presend start
option is selected.
0x0
0x1
Set this bit to one to cause the DMA transfer engine to send a NAK on the last byte.
0x0
0x1
Always set this bit field to zero.
Set this bit to one to enable the master state machine to monitor the start conditions generated by other
masters. The bus is assumed to be busy from the first start condition generated by another master until a
stop condition is generated.
0x0
0x1
This bit is set to one by the I2C controller state machines. It holds the I2C clock line low until cleared. It
must be cleared by firmware, either by CPU instructions or DMA PIO transactions. It is set high when a
slave address is matched by the slave controller. It is also set high at the end of a master or slave transaction
that had the RETAIN_CLOCK bit set high. Software should not set this bit to one.
0x0
0x1
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SNAK — slave not acknowledge when the held clock is released.
ACK — slave acknowledge when the held clock is released.
ACK_IT — Send an ACK on the last byte received.
NAK_IT — Send a NAK on the last byte received.
SINGLE — Assume we are the only master.
MULTIPLE — Enable multiple master bus busy monitoring from start detects.
RELEASE — Release the clock line.
HELD_LOW — The clock line is currently being held low.
28
12
0
0
HW_I2C_QUEUECMD field descriptions
PRE_
ACK
27
11
8005_8000h base + 80h offset = 8005_8080h
0
0
26
10
0
0
25
0
0
9
XFER_COUNT
24
0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0