MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet
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MCIMX281AVM4B
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MCIMX281AVM4B Summary of contents
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... Freescale Semiconductor Application Note i.MX28 Layout and Design Guidelines This application note describes proper design, placement, and PCB routing techniques for the i.MX28 processor. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: AN4215 Rev. 0, 09/2010 CONTENTS 1. PCB Stack- PCB Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ...
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... Power Planes Split the power plane layer into separate VDDD (digital core), VDDA (analog supply), and VDDIO (digital I/O supply) power planes. The example layout below shows a VDDD and VDDIO plane split. 2 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... Use at least two ground vias immediately next to the DCDC_GND pin. The DCDC_GND pin switches large amounts of current at a high frequency; decreasing the impedance to the ground plane reduces DCDC converter noise and increases stability. Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 PMU and DC-DC Converter ...
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... Place the DCDC inductor as close as possible to the DCDC_LP and DCDC_LN pins. • Route the inductor traces close together. 4 VDDIO BATTERY i.MX i.MX28 Layout and Design Guidelines, Rev. 0 VDDIO LOOP2 Current loop during inductor discharge. DCDC_GND DCDC_BATT i.MX Freescale Semiconductor ...
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... A thicker trace may be required for longer battery trace runs (using a plane is best). • Connect the negative battery terminal directly to the ground plane(s) as well as to the top and bottom ground fill using multiple vias (3 or more). Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 PMU and DC-DC Converter 5 ...
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... These rules apply to both the 24.000 MHz and 32.768 kHz crystal circuits. The drawing below shows an example layout for the 24.000 MHz crystal circuit. In this drawing, all circuit components are routed on the top layer above a ground plane. 6 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... DRAM supply pins and/or DRAM memory supply pins. Something as simple as the layout engineer using too few vias to connect the supply pins may cause the DRAM memory interface to fail. Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 DRAM Memory ...
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... Each bank has its own control signal (less loading). • Clocks (CLK, CLK#) — Differential, terminated on die with ODT. • Data mask (DQMx) — Single ended input, terminated on die with ODT. — One data mask for each byte lane. 8 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... Length must be matched within 100 mils of the corresponding data byte lane (the closer the matching, the better). — Traces routed with a 50-60 ohms single ended impedance. • DRAM clock (EMI_CLK / EMI_CLKn) — Clock pair lengths should be matched within 25 mils. Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 DRAM Memory 9 ...
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... DRAM supply voltage. Because the full edge is now on the line, full reflection occurs. So for this example, the signal traces should not exceed 2.25cm (30% of 7.5cm). This is valid for the distance between one sender and one receiver. 10 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... The routing can be achieved with low cost PCB manufacturing using 5 mils trace/space and 8/16 through-hole vias. Note that this layout shows fan-out only, differential pair routing is not complete, and does not include length matching. Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 DRAM Memory ...
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... Trace capacitance should be minimized. • Avoid crossing plane splits as this will degrade signal integrity and increase radiated emissions. • Trace length matching may be beneficial in some cases where the trace length routing is long (>3 inches). 12 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... EMI problems. • Failure to maintain parallelism – Failing to maintain parallelism will cause impedance discontinuities that will directly affect signal quality. It also contributes to the trace-length mismatch and will cause an increase in signal skew. Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 USB 13 ...
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... Must be routed with 100 ohm differential impedance and 50 ohm single ended impedance. • Must be routed over a solid ground plane to maintain a controlled impedance over the entire trace route. • Trace lengths for each pair should be matched. • Use a minimum distance of 30 mils between TX and RX pairs. 14 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... RJ45 connector, or the area between the magnetics and RJ45 connector. — A ground plane should be placed underneath the RX and TX pairs between the ethernet PHY and magnetics module as shown below. • RJ45 Jack with integrated magnetics Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 Ethernet 15 ...
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... D+/D- signal lines. However, in most cases, it should not be required if the PCB layout is satisfactory. Ideally, the common mode choke should be approved for high speed USB use or tested thoroughly to verify there are no signal integrity issues created. 16 i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... The example layout below shows a 2 layer escape route. The Allegro source layout file for this escape route is available for download from the Freescale i.MX28 support web page. Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 Industrial Design ...
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... PCB. 13 Revision History Table 1 provides the revision history for this application note. Rev. Date Number 0 09/21/2010 Initial release. 18 Table 1. Document Revision History Substantive Change(s) i.MX28 Layout and Design Guidelines, Rev. 0 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor i.MX28 Layout and Design Guidelines, Rev. 0 Revision History 19 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...