MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1092

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Core Command Queue with Placement Logic
14.6.1.3 Write Buffer Collision
Incoming write requests in the command queue are allocated to one of the four write buffers
of the core logic automatically based on availability. New write commands will be designated
to any of the available buffers. However, back-to-back write requests from a particular
source ID will be allocated to the same write buffer as the previous command.
Since the core logic must pull data out of the buffers in the order it was stored, if a write
command is linked to a buffer that is associated with another command in the queue, then
the new command will be placed in the command queue after that command, regardless of
priority. This feature will always be enabled.
14.6.1.4 Priority
Priorities are used to distinguish important commands from less important commands. Each
command is given a priority based on the command type through the programmable
parameters axiY_r_priority and axiY_w_priority (where Y represents the port number). A
priority value of 0 is the highest priority, and a priority value of 7 is the lowest priority.
The placement algorithm will attempt to place higher priority commands ahead of lower
priority commands, as long as they have no source ID, write buffer or address collisions.
Higher priority commands will be placed lower in the command queue if they access the
same address, are from the same requestor or use the same buffer as lower priority commands
already in the command queue.
14.6.1.5 Bank Splitting
Before accesses can be made to two different rows within the same bank, the first active
row must be closed (pre-charged) and the new row must be opened (activated). Both activities
require some timing overhead; therefore, for optimization, the placement queue will attempt
to insert the new command into the command queue such that commands to other banks
may execute during this timing overhead. The placement of the new commands will still
follow priority, source ID, write buffer and address collision rules.
The placement logic will also attempt to optimize the core logic by inserting a command
to the same bank as an existing command in the command queue immediately after the
original command. This reduces the overall timing overhead by potentially eliminating one
pre-charging/activating cycle. This placement will only be possible if there are no priority,
source ID, write buffer or address collisions or conflicts with other commands in the
command queue.
All bank splitting features are enabled through the bank_split_en parameter.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1092
Freescale Semiconductor, Inc.