MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 545
MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
- Current page: 545 of 2327
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7.5.28 APBX DMA Channel 3 Next Command Address Register
The APBX DMA Channel 3 next command address register points to the next multiword
command to be executed. Commands are threaded on the command address. Set CHAIN
to one to process command lists.
Because channel 3 is not assigned to any peripheral, this register is of no practical usage
and just reserved for compatibility.
Address:
Re-
7.5.29 APBX DMA Channel 3 Command Register (HW_APBX_CH3_CMD)
The APBX DMA Channel 3 command register specifies the cycle to perform for the current
command chain item.
Because channel 3 is not assigned to any peripheral, this register is of no practical usage
and just reserved for compatibility.
Freescale Semiconductor, Inc.
set
Bit
W
R
CMD_ADDR
31
0
Field
31 0
30
0
29
0
(HW_APBX_CH3_NXTCMDAR)
HW_APBX_CH3_NXTCMDAR
28
0
Pointer to next command structure for channel 3.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_APBX_CH3_NXTCMDAR field descriptions
24
0
23
0
22
0
21
0
20
0
8002_4000h base + 260h offset = 8002_4260h
19
0
18
0
17
CMD_ADDR
0
Chapter 7 AHB-to-APBX Bridge with DMA (APBX-Bridge-DMA)
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
545
0
0
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