MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2217

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
Freescale Semiconductor, Inc.
Reset
Reset
OVERFLOW_IRQ
FIFO_SERVICE_
UNDERFLOW_
DMA_PREQ
PRESENT
Bit
Bit
W
W
RSRVD2
RSRVD1
R
R
30 17
FIFO_
FIFO_
Field
15 7
IRQ
IRQ
31
16
6
5
4
31
15
1
0
HW_SAIF_STAT
30
14
0
0
This bit is set to 1 in products in which SAIF is present.
Reserved.
DMA Request Status. This read-only bit reflects the current state of the SAIF's DMA request signal. DMA
requests are issued any time the request signal toggles.
Reserved.
This bit is set by hardware if the FIFO underflows during SAIF operation. Underflow occurs whenever a read
or pop is attempted on an empty FIFO. This occurs in transmit mode when the FIFO is not filled in time and
the hardware tries to pop a sample from the bottom of the FIFO. It also occurs in receive mode when the
DMA or software attempts to read data from an empty FIFO. Reset this bit by writing a one to the SCT clear
address space and not by a general write.
This bit is set by hardware if the FIFO overflows during SAIF operation. Overflow occurs whenever a write
or push is attempted to a full FIFO. This occurs in transmit mode if the FIFO is full and software or the DMA
attempts to write additional data to the top of the FIFO. It also occurs in receive mode when the DMA or
software does not respond in time to a service request, and the hardware attempts to push data to a full
FIFO. Reset this bit by writing a one to the SCT clear address space and not by a general write.
This bit is set by hardware when the FIFO requires service. FIFO service requests are made when an empty
entry exists during transmit or a full entry exists during receive. A DMA request is generated (DMA_PREQ
toggles) each time this bit is set. Once the DMA or software has serviced the request and the FIFO is filled
(TX) or emptied (RX), this bit is automatically cleared. This interrupt can be used by software to trigger the
manual movement of samples from/to the SAIF's FIFO to/from a memory buffer when the SAIF's DMA
channel is not used.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
8004_2000h base + 10h offset = 8004_2010h
RSRVD1
HW_SAIF_STAT field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
24
RSRVD2
0
0
8
Description
23
0
0
7
22
0
0
6
Chapter 35 Serial Audio Interface (SAIF)
21
0
5
0
20
0
4
0
19
0
0
3
RSRVD0
18
0
0
2
17
0
0
1
BUSY
2217
16
0
0
0