MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2211

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 35 Serial Audio Interface (SAIF)
When the programmed data size is smaller than the frame size or number of BITCLKs per
LRCLK, there are BITCLK periods within the sample frame in which no data is being
transmitted or received. This occurs in 48xFs mode when that data is less than 24 bits, and
2
for all data sizes allowed in 64xFs mode. For LJ and I
S modes, this occurs after the sample
has been transmitted or received, while for RJ mode, this occurs prior to the sample being
transmitted or received.
For 16-bit (32xFs mode) operation and 24-bit (48xFs mode) operation, data is always being
2
transmitted, so that LJ and RJ modes are identical. I
S is a special case for these modes. At
the start of transmit or receive, the first BITCLK period after LRCLK transitions is a null
or wait state cycle in which no PCM data is present. However, this means one too few
BITCLK periods remain to transmit or receive data before LRCLK transitions. As a result,
the protocol dictates that the last serial PCM bit of each sample be transmitted or received
during the BITCLK wait state at the start of the next sample.
Another format, the DSP Compatible Serial Interface Format, is now supported by the
SAIF module. In DSP format, the Right channel data immediately follows the left channel
data as in 16 and 24 bit operation with BITCLK being 32xFs and 48xFs respectively. This
format is one of the type where a synch pulse on the LRCLK is followed by a left and right
data pair. The pulse is 1 BITCLK clock cycle wide, as oppose to 16 or 24 BITCLK clock
cycles in the other formats. DSP format has 2 data modes: A and B. Mode A resembles LJ
format where the first bit is aligned with the LRCLK pulse. Mode B resembles I2S format
where the first bit is delayed by 1 BITCLK cycle.
Additionally data can be programmed to be transmitted or received MSB or LSB first. The
bits to program frame format reside within the HW_SAIF_CTRL register.
35.2.7 Pin Timing
The figure below shows the six basic frame formats supported by the SAIF. Keep in mind
that for 16-bit operation, BITCLK runs at either 32x or 48x the sample rate, and for 17-bit
through 24-bit operation, it runs at either 48x or 64x the sample rate (that is, the clock
frequency relationship of differing data sizes is not shown here).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
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