MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1567

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

then will be written to the MB. If the MB is not unlocked in time and yet another new
message with the same ID arrives, then the new message overwrites the one on the SMB
and there will be no indication of lost messages either in the Code field of the MB or in the
Error and Status Register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code
field is asserted. If the ARM reads the Control and Status word and finds out that the BUSY
bit is set, it should defer accessing the MB until the BUSY bit is negated.
Deactivation takes precedence over locking. If the ARM deactivates a locked Rx MB, then
its lock status is negated and the MB is marked as invalid for the current matching round.
Any pending message on the SMB will not be transferred anymore to the MB.
25.4.9 Rx FIFO
The receive-only FIFO is enabled by asserting the FEN bit in the MCR. The reset value of
this bit is zero to maintain software backwards compatibility with previous versions of the
module that did not have the FIFO feature. When the FIFO is enabled, the memory region
normally occupied by the first 8 MBs ($80-$FF) is now reserved for use of the FIFO engine
(see
FIFO engine. The ARM can read the received frames sequentially, in the order they were
received, by repeatedly accessing a Message Buffer structure at the beginning of the memory.
The FIFO can store up to 6 frames pending service by the ARM. An interrupt is sent to the
ARM when new frames are available in the FIFO. Upon receiving the interrupt, the ARM
must read the frame (accessing an MB in the $80 address) and then clear the interrupt. The
act of clearing the interrupt triggers the FIFO engine to replace the MB in $80 with the next
frame in the queue, and then issue another interrupt to the ARM. If the FIFO is full and
more frames continue to be received, an OVERFLOW interrupt is issued to the ARM and
subsequent frames are not accepted until the ARM creates space in the FIFO by reading
one or more frames. A warning interrupt is also generated when 4frames are accumulated
in the FIFO.
A powerful filtering scheme is provided to accept only frames intended for the target
application, thus reducing the interrupt servicing work load. The filtering criteria is specified
by programming a table of 8 32-bit registers that can be configured to one of the following
formats (see also
Freescale Semiconductor, Inc.
• Format A: 8 extended or standard IDs (including IDE and RTR)
Rx FIFO
If the BUSY bit is asserted or if the MB is empty, then reading the
Control and Status word does not lock the MB.
Structure). Management of read and write pointers is done internally by the
Rx FIFO
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Structure):
Note
Chapter 25 Controller Area Network (FlexCAN)
1567