MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1117

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.8.10 DRAM Control Register 09 (HW_DRAM_CTL09)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
CONTROLLER_
W
R
REFRESH_IN_
CKE_STATUS
Q_ALMOST_
SREFRESH_
USER_DEF_
USER_DEF_
COMMAND_
REG_RO_0
ACCEPTED
REG_RO_1
PROCESS
31
0
BUSY
FULL
31 9
Field
Field
31 0
ACK
3 0
30
8
7
6
5
4
0
29
0
HW_DRAM_CTL09
28
0
User-defined input register 0.
Holds the value driven to the MC by the PHY on the signals param_user_def_reg_ro_X (where X ranges
from 0 to 7) at the EMI core level. There are a total of 8 user-defined input registers.
Status signal from the EMI. This will only be low when the EMI is not reading data, writing data or processing
a command.
Active-high signal that indicates that the EMI is executing a refresh command. This signals is asserted when
a refresh command is sent t othe DRAM devices and the remains asserted until the refresh command has
completed.
Indicates that the queue has reached the value set in the q_fullness parameter in the controller.
Acknowledge signal that indicates that the memory devices are in self-refresh mode. This signal will only
be asserted if the DRAMs have been placed into self-refresh mode through the assertion of the srefresh_enter
signal and if the signal is still held high until the memory enters self-refresh mode.
Indicates the memory devices are in either their self-refresh or power-down mode. This signals is the status
of the control_cke signal inside the EMI, but may be delayed through the cke_delay paramter in the contoller
to reflect the inverted CKE status on the memory bus. NOTE: this parameter is inverted with respect to the
logic state on the external CKE pin.
Indicates when bus interface commands are accepted.
User-defined input register 1.
Holds the value driven to the MC by the PHY on the signals param_user_def_reg_ro_X (where X ranges
from 0 to 7) at the EMI core level. There are a total of 8 user-defined input registers.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
HW_DRAM_CTL08 field descriptions
HW_DRAM_CTL09 field descriptions
800E_0000h base + 24h offset = 800E_0024h
22
0
21
0
20
0
19
0
USER_DEF_REG_RO_1
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1117
0
0