MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1040

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
13.3.16 DCP Channel 0 Command Pointer Address Register
The DCP channel 0 current command address register points to the multiword descriptor
that is to be executed (or currently being executed). The channel may be activated by writing
the command pointer address to a valid descriptor in memory and then updating the
semaphore to a non-zero value. After the engine completes processing of a descriptor, the
next_ptr field from the descriptor is moved into this register to enable processing of the
next descriptor. All channels with a non-zero semaphore value will arbitrate for access to
the engine for the subsequent operation.
DCP Channel 0 is controlled by a variable sized command structure. This register points
to the command structure to be executed.
EXAMPLE
pointer
Address:
Re-
13.3.17 DCP Channel 0 Semaphore Register (HW_DCP_CH0SEMA)
The DCP Channel 0 semaphore register is used to synchronize the CPU instruction stream
and the DMA chain processing state. After a command chain has been generated in memory,
software should write the address of the first command descriptor to the CMDPTR register
and then write a non-zero value to the semaphore register to indicate that the channel is
active. Each command packet has a chaining bit which indicates that another descriptor
should be loaded into the channel upon completion of the current descriptor. If the chaining
bit is not set, the next address will not be loaded into the CMDPTR register. Each packet
1040
set
Bit
W
R
31
0
ADDR
Field
31 0
30
0
29
0
HW_DCP_CHnCMDPTR_WR(0, v);
pCurptr = (hw_DCP_chncmdptr_t *) HW_DCP_CHnCMDPTR_RD(0);
HW_DCP_CH0CMDPTR
(HW_DCP_CH0CMDPTR)
28
0
Pointer to descriptor structure to be processed for channel 0.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_DCP_CH0CMDPTR field descriptions
23
0
22
0
8002_8000h base + 100h offset = 8002_8100h
21
0
20
0
19
0
// Write channel 0 command pointer
18
0
17
0
ADDR
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
// Read current command
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0