MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1650

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

PHY Management Interface
Note that overflow is a fatal error and must be addressed by resetting the core or deasserting
the ECR(ETHER_EN) bit to clear the FIFOs and prepare for normal operation again.
26.3.16.3 Receive FIFO Overflow
If, during a frame reception the client application is not able to receive data , the MAC
receive control, when the FIFO reaches the programmable almost full threshold truncates
the incoming frame (To avoid a overflow). The frame is subsequently received on the FIFO
interface with an error indication (ME of
with the truncation error status bit (TR of
'1'.
26.3.17 PHY Management Interface
26.3.17.1 Overview
The MDIO interface is a two-wire Management Interface. The MDIO management interface
implements a standardized method to access the PHY device management registers. This
is a Master MDIO interface, which can be connected to up to 32 PHY devices.
26.3.17.2 MDIO Frame Format
The MDIO Master controller communicates with the Slave (PHY device) using Frames,
which are defined in
bit preamble, 14 bit command, 2 bit bus direction change, 16 bit data). Each bit is transferred
with the rising edge of the MDIO clock (MDC signal). The PHY Management interface
supports the standard MDIO specification (IEEE803.2 Clause 22).
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Type
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 26-26. MDIO Frame Formats (Read / Write)
Figure 26-24. Receive FIFO Overflow Protection
Table
GMII /MII Receive
gmii/mii_rx_data
gmii/mii_rx_en
gmii/mii_rx_err
Receive FIFO
ff_rx_err_stat
ff_rx_dsav
ff_rx_data
ff_rx_dval
ff_rx_sop
ff_rx_eop
ff_rx_rdy
ff_rx_clk
ff_rx_err
rx_clk
26-26. A complete frame has a length of 64 bits (Optional 32
1
Command
Enhanced uDMA Receive Buffer Descriptor
Legacy FEC Receive Buffer
2
3
Freescale Semiconductor, Inc.
Descriptor) set to
)