MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1765

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
Freescale Semiconductor, Inc.
Reset
Reset
WR_THRESH
PIO_QUEUE_
QUEUE_RUN
RD_THRESH
RD_QUEUE_
WR_CLEAR
RD_CLEAR
Bit
Bit
W
W
R
R
IRQ_EN
RSVD3
RSVD2
RSVD1
MODE
31 21
20 16
15 13
Field
12 8
7 6
5
4
3
2
1
31
15
0
0
RSVD2
HW_I2C_QUEUECTRL
30
14
0
0
Always set this bit field to zero.
This field specified the threshold value of the number of read queue words, or more, that should be in the
queue before a read queue interrupt is generated to the CPU. The valid range for this field is 0-7. A value
of 0 indicates a threshold of an empty queue.
Always set this bit field to zero.
This field specified the threshold value of the number of write queue words, or less, that should be in the
queue before a write queue interrupt is generated to the CPU. The valid range for this field is 0-8. A value
of 0 indicates a threshold of an empty queue.
Always set this bit field to zero.
Asserting this bit essentially tells the system to begin executing commands and data that are in the queue.
This allows software to kick off a series of commands when it chooses.
0x0
0x1
Asserting this bit clears the read queue that holds data read from the I2C port.
Asserting this bit clears the write queue that holds commands and data written through the QUEUECTRL
and DATA registers.
When this bit is set writes to the QUEUECTRL and DATA registers are queued up. When the
HW_I2C_QUEUECTRL_QUEUE_RUN bit is later set, all the commands (and associated data) will be
executed in the order they are written.
Set this bit to one to enable receiving interrupts from the RD_QUEUE_IRQ source to the interrupt collector.
Set to zero to disable interrupts from the I2C controller.
0x0
0x1
29
13
0
0
STOP — Don't process commands or stop after processing the currently executing command.
START — Start processing commands.
DISABLED — Interrupt source disabled.
ENABLED — Interrupt source enabled.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_I2C_QUEUECTRL field descriptions
27
11
0
0
8005_8000h base + 60h offset = 8005_8060h
WR_THRESH
RSVD3
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
RSVD1
22
0
0
6
21
0
5
0
20
0
4
0
19
0
0
3
Chapter 27 Inter IC (I2C)
RD_THRESH
18
0
0
2
17
0
0
1
1765
16
0
0
0