MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1289

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
Freescale Semiconductor, Inc.
Reset
Reset
DEBUGSYNDROME
M2M_ENCODE
M2M_ENABLE
M2M_LAYOUT
Bit
Bit
W
W
R
R
CLKGATE
SFTRST
RSVD5
RSVD4
29 23
21 20
19 18
Field
31
15
31
30
22
17
16
1
0
HW_BCH_CTRL
30
14
1
0
RSVD3
Set this bit to zero to enable normal BCH operation. Set this bit to one (default) to disable clocking with
the BCH and hold it in its reset (lowest power) state. This bit can be turned on and then off to reset the
BCH block to its default state. This bit resets all state machines except for the AHB master state machine
0x0
0x1
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
0x0
0x1
Reserved, always set this bit to zero.
(For debug purposes only). Enable write of computed syndromes to memory on BCH decode operations.
Computed syndromes will be written to the auxiliary buffer after the status block. Syndromes will be
written as padded 16-bit values.
Reserved, always set these bits to zero.
Selects the flash page format for memory-to-memory operations.
Selects encode (parity generation) or decode (correction) mode for memory-to-memory operations.
NOTE! WRITING THIS BIT INITIATES A MEMORY-TO-MEMORY OPERATION. The BCH module must
be inactive (not processing data from the GPMI) when this bit is set. The M2M_ENCODE and
M2M_LAYOUT bits as well as the ENCODEPTR, DATAPTR, and METAPTR registers are used for
memory-to-memory operations and must be correctly programmed before writing this bit.
29
13
1
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RUN — Allow BCH to operate normally.
RESET — Hold BCH in reset.
RUN — Allow BCH to operate normally.
NO_CLKS — Do not clock BCH gates in order to minimize power consumption.
28
12
0
0
8000_A000h base + 0h offset = 8000_A000h
HW_BCH_CTRL field descriptions
27
11
0
0
RSVD5
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
Chapter 16 20-BIT Correcting ECC Accelerator (BCH)
0
0
7
22
0
0
6
RSVD1
21
0
5
0
RSVD4
20
0
4
0
19
0
0
LAYOUT
3
M2M_
18
0
0
2
17
0
0
1
1289
16
0
0
0