MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1556

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Message Buffer Structure
Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is
received from the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted
within the frame.
25.3.1 Rx FIFO Structure
When the FEN bit is set in the MCR, the memory area from $80 to $FF (which is normally
occupied by MBs 0 to 7) is used by the reception FIFO engine.
FIFO data structure. The region $0-$C contains a MB structure which is the port through
which the CPU reads data from the FIFO (the oldest frame received and not read yet). The
region $10-$DF is reserved for internal use of the FIFO engine. The region $E0-$FF contains
an 8-entry ID table that specifies filtering criteria for accepting frames into the FIFO.
25-5
depending on the IDAM field of the MCR. Note that all elements of the table must have
the same format. See
1556
$DF
$E0
$E4
$E8
$EC
$FC
$10
$F0
$F4
$F8
$C
$0
$4
$8
to
31
shows the three different formats that the elements of the ID table can assume,
Data Byte 0
Data Byte 4
28
27
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
ID (Standard/Extended)
Rx FIFO
24
SRR
22
Table 25-4. Rx FIFO Structure
for more information.
IDE
21
Data Byte 1
Data Byte 5
RTR
20
= Unimplemented or Reserved
19
LENGTH
ID Table 0
ID Table 1
ID Table 2
ID Table 3
ID Table 4
ID Table 5
ID Table 6
ID Table 7
Reserved
16
15
Data Byte 2
Data Byte 6
ID (Extended)
Table 25-4
TIME STAMP
Freescale Semiconductor, Inc.
8
7
shows the Rx
Data Byte 3
Data Byte 7
Table
0