MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 118

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Operation
3.2 Operation
The DFLPT provides the following features as part of the memory management within the
i.MX28 embedded software system:
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• 16-Kbyte AHB slave located at addresses 0x800C_0000–0x800C_3FFF supports the
• Sixteen fully programmable (value and location) page table entries. All 32-bits are
required 4K L1 PTEs. To use the DFLPT, point the ARM TTB to 0x800C_0000.
programmable. The location/binding of each MPTE is determined through the
HW_DIGCTL_MPTEn_LOC register fields in the DIGCTL module. The span (1-128
MB) of MPTE is determined through the HW_DIGCTL_MPTEn_SPAN register fields
in the DIGCTL module. In addition, each of the sixteen entries can be disabled through
HW_DIGCTL_MPTEn_DIS if less than sixteen entries are required (this avoids the
need to bind an entry to some unused area of physical memory):
• Only 32-bit word accesses are supported.
• All AHB burst types are supported.
• Each access has a fixed 1-cycle AHB wait state.
• Bus errors are supported when accessing an unbound PTE (that is, an address not
• When an entry is disabled (through HW_DIGCTL_MPTEn_DIS), it cannot be
• A read from an unbound PTE returns 0x0000_0000. When the MMU is enabled,
• When using the span feature, the entire span is bound to the MPTE. This means
• A write to an un-bound PTE shall result in a slave error, which shall in turn result
• Each MPTE has a reset value of 0x0000_0000.
bound to an MPTE or spanned MPTE).
bound, so programming its HW_DIGCTL_MPTEn_LOC field has no effect. This
means that another entry which is not disabled (HW_DIGCTL_MPTEn_DIS=0)
can have the same value for HW_DIGCTL_MPTEn_LOC as the disabled entry.
this results in a section translation fault if the read is the result of a page-walk.
that up to 128 32-bit word locations/addresses can be bound to any MPTE (see
below for a more detailed explanation).
in an ARM data-abort. Note that when writing to a PTE encompassed in a span,
the descriptor will apply to the span of the MPTE with the exception of the
base-address, which only applies to the base MPTE (at location LOC). Subsequent
base addresses within a span are generated linearly from this LOC value (see below).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.