MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2119

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Internally, all image data is handled as 32bpp data (either RGB or YUV, depending on
output mode selection) for all steps after the color space conversion. Input RGB images are
always converted to the equivalent 32bpp format before processing.
34.1.2 Block Size Selection
The PXP can be configured to process blocks that are either 8x8 pixels or 16x16 pixels.
The granularity of image size and location of video or overlay buffers within the final
destination frame buffer has twice the precision when selecting 8x8 pixel block sizes. When
selecting a 16x16 pixel block size, the accesses to fetch S0 and S1 images and write the
final frame buffer are more efficient since twice as much data is requested and processed
per memory request. When optimizing the system for memory bandwidth and image
processing time, configure the PXP to process 16x16 pixel blocks.
The control registers that are in block size units need to be programmed consistently with
the BLOCK_SIZE control bit setting. If the source image is 32x32 pixels, then the width
and height setting will be 4 when selecting 8x8 pixel block size and 2 when selecting 16x16
block size.
34.1.3 PXP Limitations/Issues
Freescale Semiconductor, Inc.
• 16-bit RGB in either 565, 555, or 1555 format
• YUV 4:4:4/4:2:2 1-plane
• YUV 4:2:2/4:2:0 2-plane
• Interlaced output processing
• The PXP's scalar uses a bilinear scaling algorithm and can scale YUV images from
• When using the NEXT register, the interrupt enable setting should remain the same for
• The PXP cannot rotate/flip video in the interlaced modes.
• When performing input interlacing, the input image and overlays must be multiples of
1/4x to 4096x in 12-bit fractional steps.
all frames. If not, the PXP will change the interrupt enable register value and possibly
cause the loss of an interrupt.
8x16 (in 8x8 block size mode) or 16x32 (16x16 pixel blocks) pixels. Overlays must
also reside on the same boundaries.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 34 Pixel Pipeline (PXP)
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