MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1948

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
30.4.4 UART Line Control Register (HW_UARTAPP_LINECTRL)
HW_UARTAPP_LINECTRL: 0x030
HW_UARTAPP_LINECTRL_SET: 0x034
HW_UARTAPP_LINECTRL_CLR: 0x038
HW_UARTAPP_LINECTRL_TOG: 0x03C
The UART Line Control Register contains integer and fractional part of the baud rate divisor
value. It also contains the line control bits.
Address:
Re-
1948
set
Bit
BAUD_DIVFRAC
W
R
BAUD_DIVINT
31
UARTEN
0
SIREN
SIRLP
31 16
15 14
RSVD
WLEN
Field
Field
13 8
SPS
6 5
30
2
1
0
7
0
29
0
HW_UARTAPP_LINECTRL
28
0
IrDA SIR Low Power Mode. Unsupported.
SIR Enable. Unsupported.
UART Enable. If this bit is set to 1, the UART is enabled. Data transmission and reception occurs for the
UART signals. When the UART is disabled in the middle of transmission or reception, it completes the current
character before stopping.
Baud Rate Integer [15:0]. The integer baud rate divisor.
Reserved, do not modify, read as zero.
Baud Rate Fraction [5:0]. The fractional baud rate divisor.
Stick Parity Select. When bits 1, 2, and 7 of this register are set, the parity bit is transmitted and checked
as a 0. When bits 1 and 7 are set, and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this
bit is cleared stick parity is disabled.
Word length [1:0]. The select bits indicate the number of data bits transmitted or received in a frame as
follows: 11 = 8 bits, 10 = 7 bits, 01 = 6 bits, 00 = 5 bits.
27
0
26
0
HW_UARTAPP_CTRL2 field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BAUD_DIVINT
25
0
24
HW_UARTAPP_LINECTRL field descriptions
0
23
0
22
0
21
0
8006_A000h base + 30h offset = 8006_A030h
20
0
19
0
18
0
17
0
16
0
15
RSVD
0
Description
Description
14
0
13
0
BAUD_DIVFRAC
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0