MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1764

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
27.5.7 I2C Queue control reg. (HW_I2C_QUEUECTRL)
The I2C Control Register implements the controls for I2C PIO Queue mode.
HW_I2C_QUEUECTRL: 0x060
HW_I2C_QUEUECTRL_SET: 0x064
HW_I2C_QUEUECTRL_CLR: 0x068
HW_I2C_QUEUECTRL_TOG: 0x06C
1764
MASTER_LOSS_
IRQ_SUMMARY
IRQ_SUMMARY
IRQ_SUMMARY
IRQ_SUMMARY
EARLY_TERM_
SLAVE_STOP_
XFER_TERM_
SLAVE_IRQ_
NO_SLAVE_
OVERSIZE_
SUMMARY
SUMMARY
ACK_IRQ_
Field
5
4
3
2
1
0
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller. It is a logical AND of the
corresponding interrupt status bit and interrupt enable bit.
0x0
0x1
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_I2C_STAT field descriptions (continued)
Description
Freescale Semiconductor, Inc.