MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 980
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MCIMX281AVM4B
Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(2327 pages)
2.MCIMX283DVM4B.pdf
(20 pages)
3.MCIMX281AVM4B.pdf
(72 pages)
Specifications of MCIMX281AVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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- Download datasheet (17Mb)
NAND Boot Mode
12.12.1.1 Search Area
The search area is defined by search count times search stride.
12.12.1.2 Search Count
Search count is defined as the number of copies of BCB data structures present in a given
search area. It is 2^efNANDBootSearchCount (a value from OTP/eFuses). The default
search count when OTP is not programmed is 4. This is the most common case. The
minimum search count is 2 and the maximum search count is 32768.
12.12.1.3 Search Stride
Search stride is defined as the distance in pages between two BCB data structures in a given
search area. It is 64 pages times efNANDBootSearchStride (a value from OTP/eFuses).
When efNANDBootSearchStride is not blown, the boot ROM defaults it to 1. Therefore,
the minimum search stride is always 64 pages apart (the most common case), and the
maximum search stride is (64 * 15 = 960) pages apart.
12.12.1.4 Boot Control Blocks (BCB)
There are two BCB data structures: FCB and DBBT. As part of the NAND media
initialization, the ROM driver uses safe NAND timings to search for a Firmware
Configuration Block (FCB) that contains the optimum NAND timings, the page address of
Discovered Bad Block Table (DBBT) Search Area and the start page address of the primary
and secondary firmware.
In i.MX28, there are no separate boot modes for each type of ECC level. The hardware
ECC level to use is embedded inside FCB block. The FCB data structure is itself protected
using software ECC (SEC-DED Hamming Codes). Driver reads raw 2112 bytes of first
sector and runs through software ECC engine that determines whether FCB data is valid or
not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments the page
number to Search Stride number of pages to read for the next BCB until 2^n
efNANDBootSearchCount pages have been read.
If search fails to find a valid FCB, the NAND driver responds with an error and the boot
ROM enters into the recovery mode.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
980
Freescale Semiconductor, Inc.
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