MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2013

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Address:
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Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
RSVD1
RSVD0
31 24
23 16
PERB
PETB
Field
15 8
7 0
30
0
29
0
HW_USBCTRL_ENDPTPRIME 8008_0000h base + 1B0h offset = 8008_01B0h
RSVD1
28
0
Reserved.
Prime Endpoint Transmit Buffer.
For each endpoint, a corresponding bit is used to request that a buffer be prepared for a transmit operation
in order to respond to a USB IN/INTERRUPT transaction. Software should write a 1 to the corresponding
bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear
this bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
PETB[7] = Endpoint 7.
PETB[6] = Endpoint 6.
PETB[5] = Endpoint 5.
PETB[4] = Endpoint 4.
PETB[3] = Endpoint 3.
PETB[2] = Endpoint 2.
PETB[1] = Endpoint 1.
PETB[0] = Endpoint 0.
Reserved.
Prime Endpoint Receive Buffer.
For each endpoint, a corresponding bit is used to request a buffer be prepared for a receive operation for
when a USB host initiates a USB OUT transaction. Software should write a 1 to the corresponding bit
whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear
this bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by hardware during hardware re-priming operations when a dTD
is retired, and the dQH is updated.
PERB[7] = Endpoint 7.
PERB[6] = Endpoint 6.
PERB[5] = Endpoint 5.
PERB[4] = Endpoint 4.
PERB[3] = Endpoint 3.
PERB[2] = Endpoint 2.
PERB[1] = Endpoint 1.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_USBCTRL_ENDPTPRIME field descriptions
24
0
23
0
22
0
21
0
PETB
20
0
19
0
18
0
17
0
Chapter 31 USB High-Speed On-the-Go Host Device Controller
16
0
15
0
Description
14
0
13
0
RSVD0
12
0
11
0
10
0
0
9
0
8
0
7
0
6
0
5
PERB
0
4
3
0
0
2
0
1
2013
0
0