MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1481

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

HW_RTC_CTRL_SFTRST bit. Otherwise, some of the write data could be lost because
the shadow registers could be powered down/reset before the new values can be copied to
the persistent master storage.
Registers are copied between the digital and analog sides one by one and in 32-bit words.
There are no hardwired uses for any of the bits of Persistent registers 1 through 5. Therefore,
the bits in these registers can be defined and set by the software. Persistent Register 0 is
reserved for hardware programming and configuration.
Before a new value is written to a shadow register by the CPU, software must first confirm
that the corresponding bit of HW_RTC_STAT_NEW_REGS is 0. This ensures that a value
previously written to the register has been completely handled by the copy state machine.
Failure to obey this constraint could cause a newer updated value to be lost.
NOTE: The HW_RTC_CTRL_SUPPRESS_COPY2ANALOG diagnostic bit is never set
while any copy or update operation is underway. Doing so will result in undefined operation
of the copy controller.
Figure 22-3
write to any register whose HW_RTC_STAT_NEW_REGS bit is 0 even if the copy
controller is currently busy copying a different register. For example, if the copy controller
is busy copying Persistent Register 1 from a previous write, software can simultaneously
write to Persistent Register 0 during this copy. After the copy controller has finished copying
register 1, it will then, in turn, begin the copy process for the new value of Register 0.
Therefore, registers can thus be written in any order. Again, the main important rule that
must be followed is that the HW_RTC_STAT_NEW_REGS bit for a particular register
must be 0 before it can be written and is independent of the state of the
HW_RTC_STAT_NEW_REGS bits for the other registers.
Freescale Semiconductor, Inc.
shows the copy and test procedure for a single register. However, software can
Figure 22-3. RTC Writing to a Master Register from CPU
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_RTC_PERSISTENT2_WR(0xdeadbeef);
TestValue = HW_RTC_STAT _NEW_REGS
TestValue =HW_RTC_STAT_NEW_REGS
NO
NO
rtc_write2master
TestValue == 0
TestValue == 0
Return
YES
Chapter 22 Real-Time Clock Alarm Watchdog Persistent Bits
How to write a master
register.
Extract corresponding bit.
Wait for previous write
to this register to
complete.
Write new value to shadow
that will be automatically
copied to analog side. Use
this same technique for
milliseconds, alarm, or other
persistent registers.
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