MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1103

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

The delay compensation circuitry relies on a master/slave approach. There is a master delay
line which is used to determine how many delay elements constitute a complete cycle. This
count is used, along with the programmable fractional delay settings, to determine the actual
number of delay elements to program into the slave delay lines. The master and slave delay
lines are identical. This approach allows the memory controller to observe a clock and then
delay other signals a fixed percentage of that clock. The DLL logic does not actively generate
clock signals.
The actual delay element for the delay lines is user-selectable.
The following figure shows the block diagram for a digital DLL.
Freescale Semiconductor, Inc.
• Programmable write data delays specified as percentages of a clock cycle.
• Delay compensation circuit re-sync circuitry activated during refresh cycles to
• Separate delay chains for each read DQS signal from the DRAM devices.
compensate for temperature and voltage drift.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 14 External Memory Interface (EMI)
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