MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 2016

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
31.7.39 Endpoint Complete Register
This register is used in device-mode only.
endpoint complete
Address:
Re-
2016
set
Bit
W
R
31
0
RSVD0
RSVD1
ERBR
31 24
Field
15 8
Field
7 0
30
0
29
0
HW_USBCTRL_ENDPTCOMPLETE
01BCh
RSVD1
(HW_USBCTRL_ENDPTCOMPLETE)
28
0
ETBR[0] = Endpoint 0.
Reserved.
Endpoint Receive Buffer Ready.
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a 1 by the
hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register.
There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating
ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the
ENDPTFLUSH register.
Note: These bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
ERBR[7] = Endpoint 7.
ERBR[6] = Endpoint 6.
ERBR[5] = Endpoint 5.
ERBR[4] = Endpoint 4.
ERBR[3] = Endpoint 3.
ERBR[2] = Endpoint 2.
ERBR[1] = Endpoint 1.
ERBR[0] = Endpoint 0.
Reserved.
27
0
HW_USBCTRL_ENDPTSTAT field descriptions (continued)
26
0
HW_USBCTRL_ENDPTCOMPLETE field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
22
0
21
0
ETCE
20
0
19
0
8008_0000h base + 1BCh offset = 8008_
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
RSVD0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
ERCE
0
4
3
0
0
2
0
1
0
0