MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 848

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Clock Structure
10.2.3 Clock Domain Description
All major functional clock domains/branches have trunk level clock gating for power
management. The intent is to gate clock domains off when modules of certain applications
are not necessary. This clock gating is instantiated using an ICG element from the standard
cell library. Software will have to enable the clock domain that drives on chip devices where
trunk level clock gating is implemented.
The location of ICG elements to gate clock domains is not systematic. Since most of the
clock structures throughout the system are unique, the location of ICGs for clock tree power
reduction differs from one domain to the other. The location of these ICGs to gate off clock
domains is apparent in the clock structure diagram.
All clock domains are asynchronous unless noted otherwise.
10.2.3.1 CLK_P, CLK_H
The clk_p domain is used to drive the integrated ARM9 core. The reference for clk_p can
be either ref_xtal or ref_cpu. The reference ref_cpu drives a 6-bit clock divider to provide
a maximum divide down of the reference clock by 2^6. The reference ref_xtal drives a
10-bit clock divider to provide a maximum divide down of the selected reference clock by
2^10. All of the ARM core and SoC components on the clk_h branch are considered to be
on the clk_p domain. The clk_h is actually a branch of the clk_p domain. So, clk_h runs
synchronous to clk_p.
The clk_h domain can be programmed to any divided ratio with respect to the clk_p domain
depending on performance and power requirements. A dynamic clock frequency management
controller monitors the system performance requirements and scales the clk_h frequency
to meet the performance needs. When the CPU or support components require data transfer
to/from the system memory, the frequency manager scales the clk_h domain to meet the
system performance requirements. Also, when the system is quiesced, the clk_h frequency
is reduced to save power.
The clk_h has a 5-bit divider that divides the clk_p domain to produce the clk_h domain.
The frequency for clk_h can be clk_p/32 <= clk_h <= clk_p. Two divide modes exist for
the clk_h branch:
848
• Integer divide: In this mode, the value programmed in the hw_clkctrl_hbus.div field
• Fractional divide: In this mode, the value programmed in the hw_clkctrl_hbus.div field
represents an integer divide value.
represents a binary fraction. When the accumulation of the current count and the
programmed divide value carry out of the most significant bit, a clk_h pulse is generated.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.