MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 133

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

the FSM reopens the holding register and scans for new interrupt sources. Any such IRQ
sources are presented to the CPU, provided that they are at a level higher than any currently
in-service level.
Whenever the ARM CPU takes an IRQ exception, it turns off the IRQ enable in the CPU
status register (CSR), as shown in
point, then another IRQ exception is taken.
The example in shows going from the base to a level 0 ISR. When the ISR at level 0 was
ready, it enabled IRQ interrupts. At this point, it nests IRQ interrupts up to a level 3 interrupt.
The level 3 ISR marks its in-service state, which causes the interrupt collector to open the
holding register to search for new interrupt sources. In this example, none comes in, so the
level 3 ISR completes. As part of the return process, the ISR disables IRQ interrupts, then
acknowledges the level 3 service state. This is accomplished by writing the level number
(3 in this case) to the interrupt collector's Level Acknowledge register. The interrupt collector
resets the in-service bit for level 3. If this enables an IRQ at level 3, then it asserts IRQ and
goes through the nesting process again. Since IRQ exceptions are masked in the level 3
ISR, this nesting does not take place until the level 3 ISR returns from interrupt. This return
automatically re-enables IRQ exceptions. At this point, another exception could occur.
Figure 5-4
source bit. Finally, the figure shows the point at which the level 0 ISR enters its critical
section (masks IRQ) and acknowledges level 0 to the interrupt collector and returns from
the interrupt.
Freescale Semiconductor, Inc.
shows a second nesting of the IRQ interrupt by the arrival of a level 2 interrupt
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
IRQ LEVEL 2
IRQ LEVEL 1
IRQ LEVEL 0
IRQ LEVEL 3
Figure 5-4. Nesting of Multi-Level IRQ Interrupts
CSR IRQ
Base
IRQ
Figure
5-4. If a higher priority interrupt is pending at this
Chapter 5 Interrupt Collector (ICOLL)
133