MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1050

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Programmable Registers
Each DCP channel has an 8 bit counting semaphore that is used to synchronize between
the program stream and and the DCP chain processing. DCP processing continues until the
engine attempts to decrement a semaphore that has already reached a value of zero. When
the attempt is made, the DCP channel is stalled until software increments the semaphore
count.
Address:
Re-
13.3.26 DCP Channel 2 Status Register (HW_DCP_CH2STAT)
The DCP Channel 2 Interrupt Status register contains the interrupt status bit and the tag of
the last completed operation from the command chain. If an error occurs during processing,
the ERROR bit is set and an interrupt is generated.
HW_DCP_CH2STAT: 0x1A0
HW_DCP_CH2STAT_SET: 0x1A4
HW_DCP_CH2STAT_CLR: 0x1A8
HW_DCP_CH2STAT_TOG: 0x1AC
1050
set
Bit
W
R
INCREMENT
31
0
RSVD2
RSVD1
VALUE
31 24
23 16
Field
15 8
7 0
30
0
29
0
HW_DCP_CH2SEMA
RSVD2
28
0
Reserved, always set to zero.
This read-only field shows the current (instantaneous) value of the semaphore counter.
Reserved, always set to zero.
The value written to this field is added to the semaphore count in an atomic way such that simultaneous
software adds and DCP hardware substracts happening on the same clock are protected. This bit field reads
back a value of 0x00. Writing a value of 0x02 increments the semaphore count by two, unless the DCP
channel decrements the count on the same clock, then the count is incremented by a net one.The semaphore
may be cleared by writing 0xFF to the HW_DCP_CHnSEMA_CLR register.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
HW_DCP_CH2SEMA field descriptions
0
22
0
8002_8000h base + 190h offset = 8002_8190h
21
0
VALUE
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
RSVD1
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
INCREMENT
0
5
0
4
3
0
0
2
0
1
0
0