MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 1219

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MCIMX281AVM4B

Manufacturer Part Number
MCIMX281AVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets

Specifications of MCIMX281AVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
14.8.159 DRAM Control Register 164 (HW_DRAM_CTL164)
This is a DRAM configuration register.
Address:
Re-
14.8.160 DRAM Control Register 171 (HW_DRAM_CTL171)
This is a DRAM configuration register.
Freescale Semiconductor, Inc.
set
Bit
W
R
DRAM_CLASS
OBSOLETE
31
INT_ACK
0
RSVD1
RSVD1
TMOD
31 24
23 18
Field
Field
17 8
7 4
3 0
7 0
30
0
29
0
OBSOLETE
HW_DRAM_CTL164
28
0
Always write zeroes to this field.
Defines the mode of operation of the controller.
Selects the mode of operation for the EMI.
'b0000 = DDR1
'b0001 = DDR1 with Mobile (LPDDR1)
'b0100 = DDR2
All other settings reserved.
Always write zeroes to this field.
Always write zeroes to this field.
Clear mask of the INT_STATUS parameter. WRITE-ONLY
Controls the clearing of the int_status parameter. If any of the int_ack bits are set to 'b1, the corresponding
bit in the int_status parameter will be cleared to 'b0. Any int_ack bits cleared to 'b0 will not alter the
corresponding bit in the int_status parameter. This parameter will always read back as 0x0.
Number of clock cycles after MRS command and before any other command.
Defines the number of cycles of wait time after a mode register write to any non-mode register write command.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL163 field descriptions (continued)
25
0
24
0
23
0
HW_DRAM_CTL164 field descriptions
800E_0000h base + 290h offset = 800E_0290h
22
0
RSVD1
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
INT_ACK
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
0
5
TMOD
0
4
3
0
0
2
0
1
1219
0
0

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